1. Field of the Invention
The present invention relates to a thin film semiconductor device in which bottom gate type thin film transistors each containing an active layer of polycrystalline silicon or the like are formed in an integration structure on an insulating substrate, and also a display device using a thin film semiconductor device as a driving board, and more particularly to a technique for improving the characteristics of a bottom gate type thin film transistor.
2. Description of the Related Art
A thin film semiconductor device is suitably used as a driving board for display in an active matrix type liquid crystal display or the like, and its development is being positively promoted at present. Polycrystalline silicon or amorphous silicon is used for an active layer (channel region) of a thin film transistor. Particularly, more attention is paid to the polycrystalline silicon thin film transistor because it can implement a compact and high-precision active matrix type color liquid crystal display device. According to this technique, a thin film transistor is formed as a pixel switching element on an insulating substrate formed of transparent glass or the like, and thus polycrystalline silicon thin films which are practically used as only electrode material or resistance material in a conventional semiconductor technique are used for active layers. This technique is only the technique of implementing thin film transistors for high-performance switching elements which can be produced in a high-density design to achieve such image quality as required in the market. At the same time, this technique can also implement such a design that a peripheral circuit portion which has been hitherto provided as an external IC is formed on the same board as a pixel array portion in the same process.
A top gate structure has been hitherto mainly adopted for thin film transistors. In the top gate structure, a semiconductor thin film is formed on an insulating substrate, and then a gate electrode is formed through a gate insulating film on the semiconductor thin film. In a thin film semiconductor device for a liquid crystal display, a low-cost and large-size glass plate is used as the insulating substrate.
The glass plate contains a large amount of metal impurities such as Na, etc., and thus the impurities such as Na, etc. are localized in accordance with a driving voltage for the thin film transistor. Accordingly, the characteristic of the thin film transistor is varied in accordance with the electric field due to the localization of the metal impurities. In order to countermeasure this phenomenon, a bottom gate structure has been recently developed. In the bottom gate structure, a gate electrode formed of a metal film or the like is disposed on an insulating substrate of a glass plate or the like, and then a semiconductor thin film is formed through a gate insulating film on the gate electrode. The gate electrode has an effect of shielding the electric field in the glass plate, and from the structure viewpoint, the bottom gate structure is more excellent on the point of reliability than the top gate structure.
FIG. 1 is a cross-sectional view showing a conventional thin film semiconductor device.
The thin film semiconductor device shown in FIG. 1 is achieved by integrating thin film transistors 3 having the bottom gate structure on an insulating substrate 1. For simplification of illustration, only one thin film transistor is illustrated. The thin film transistor 3 has the bottom gate structure comprising a gate electrode 5, a gate insulating film 4, a semiconductor thin film 2 and an interlayer insulating film 9 which are laminated in this order from the lower side. In the thin film transistor 3, a channel region 20 confronting the gate electrode 5, and a source region 7 and a drain region 8 which are located at both sides of the channel region 20 are formed in the semiconductor thin film 2. A stopper 6 is provided just above the channel region 20 to protect the channel region 20. The thin film transistor 3 thus formed is coated by the interlayer insulating film 9. Conductor films 10S, 10D of aluminum or the like are formed on the interlayer insulating film 9, and electrically connected to the source region 7 and the drain region 8 through contact holes formed in the interlayer insulating film 9, respectively. The conductor films 10S, 10D are subjected to a patterning treatment to serve as an electrode and a wire, respectively. When thin film semiconductor device thus formed is applied to a driving board for a display device, the thin film transistor 3 and the conductor films 10S, 10D are coated by a planarization film 12. An electrooptical material 50 such as liquid crystal or the like is superposed on a planarization film 12.
In the bottom gate type thin film transistor 3, the upper portion of the channel region 20 is coated by the interlayer insulating film 9 formed of SiO2, SiN or the like and the planarization film 12 formed of acrylic resin or the like. This structure induces no special problem in a usual case. However, if it is installed into a display device or the like, it induces a problem on reliability. That is, positive charges occur at the interface between the planarization film 12 and the electrooptical material 50 on the planarization film 12. Specifically, water or ions in the electrooptical material 50 are attracted by the potential of the gate electrode 5 or the like. These materials are trapped as the positive charges at the interface between the planarization film 12 and the electrooptical material 50. Further, the water or the ions are downwardly diffused through the planarization film 12, and the positive charges occur at the interface between the interlayer insulating film 9 and the planarization film 12. These positive charges produce a back channel in the channel region 20, so that the threshold voltage Vth of the thin film transistor 3 is varied or current leak occurs. As described above, the thin film transistor having the bottom gate structure has such an inherent factor that the characteristic thereof is varied under the effect of the external impurities in accordance with its using condition.
FIG. 2 is a schematic diagram showing an energy band of the channel region 20. The channel region 20 is sandwiched by the interlayer insulating film 9 and the gate insulating film 4 from the upper and lower sides. The channel region 20 comprises a semiconductor thin film of Si or the like, and each of the interlayer insulating film 9 and the gate insulating film 4 is formed of an SiO2, film. A metal gate electrode 5 is disposed through the gate insulating film 4 at the lower side of the channel region 20. In this system, the conductive band energy end EC has a profile indicated by a solid line of FIG. 2. Here, EF in FIG. 2 represents the Fermi level. Since EC is reduced at the gate insulating film 4 side, the original channel CH is produced along the interface between the channel region 20 and the gate insulating film 4. However, when the positive charges are stocked on the surface of the interlayer insulating film 9, EC falls at the back surface side of the interlayer insulating film 9 as indicated by a dotted line, and the back channel BCH is formed along the interface between the channel region 20 and the interlayer insulating film 9. This induces the variation of the threshold voltage and the current like to the thin film transistor having the bottom gate structure.
The present invention has been implemented to overcome the above problem, and according to an aspect of the present invention, a thin film semiconductor device comprises an insulating substrate, a plurality of thin film transistors integrated on the insulating substrate, each thin film transistor including a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, and the semiconductor thin film being formed with a channel region confronting the gate electrode, and a source region and a drain region which are located at both sides of the channel region, and a conductor film which is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region.
In the thin film semiconductor device, the conductor film is connected to the same potential as the source region or the drain region.
In the thin film semiconductor device, the conductor film is connected to a potential which is different from that of the source region or the drain region.
In the above thin film semiconductor device, the different potential is a gate potential.
In the above thin film semiconductor device, the different potential is a floating potential.
In the above thin film semiconductor device, the conductor film has a width dimension larger than that of the channel region.
In the above thin film semiconductor device, the conductor film is overlapped with a portion smaller than the overall length of the channel region.
In the above thin film semiconductor device, the thin film transistor includes a pair of channel regions which confront a pair of gate electrodes and formed in the semiconductor thin film, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with at least one of the channel regions.
According to another aspect of the present invention, a display device having a pair of insulating substrates which are connected to each other through a predetermined gap, and electrooptical material held in the gap, comprises a counter electrode formed in one of the insulating substrates, and a plurality of pixel electrodes and a plurality of thin film transistors which are integrated on the other insulating substrate, wherein each thin film transistor comprises a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, the semiconductor thin film is formed with a channel region confronting the gate electrode, and a source region and a drain region located at both sides of the channel region, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region.
In the above display device, the conductor film is connected to the same potential as the source region or the drain region.
In the above display device, the conductor film is connected to a potential which is different from that of the source region or the drain region.
In the above display device, the different potential is a gate potential.
In the above display device, the different potential is a floating potential.
In the above display device, the conductor film has a width dimension larger than that of the channel region.
In the above display device, the conductor film is overlapped with a portion smaller than the overall length of the channel region.
In the above display device, the thin film transistor includes a pair of channel regions which confront a pair of gate electrodes and are formed in the semiconductor thin film, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with at least one of the channel regions.
According to the present invention, the upper portion of the channel region is covered by the conductor film. Therefore, when positive charges are supplied from the outside, the channel region is electrically shielded by the potential of the conductor film, so that no back channel is formed. Accordingly, the variation of the threshold voltage and the current leak of the thin film transistor having the bottom gate structure can be suppressed.